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silego technology, inc. rev 1.06 000-0046110-106 revised october 10, 2017 greenpak programmable mixed signal matrix slg46110 block diagram features ? logic & mixed signal circuits ? highly versatile macrocells ? 1.8 v (5%) to 5 v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? pb-free 12-pin stqfn: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics pin configuration gnd gpio gpio gpio gpio gpio 2 3 4 7 8 9 10 gpi vdd 1 stqfn-12 (top view) gpio nc 5 6 gpio nc 11 12 3-bit lut3_4 or pipe delay vref rc oscillator pin 1 vdd pin 2 gpi pin 3 gpio pin 4 gpio pin 12 gpio pin 11 nc pin 5 nc pin 6 gpio pin 8 gpio pin 7 gnd pin 10 gpio pin 9 gpio acmp0 acmp1 look up tables (luts) counters/delay generators cnt0 cnt3 cnt1 2-bit lut2_2 3-bit lut3_3 2-bit lut2_3 3-bit lut3_2 combination function macrocells 2-bit lut2_0 or dff0 2-bit lut2_1 or dff1 3-bit lut3_1 or dff3 3bit lut3_0 or dff2 4-bit lut4_0 or cnt2 filter_0/prog. delay additional combination functions por bandgap
000-0046110-106 page 1 of 81 slg46110 1.0 overview the slg46110 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macrocells of the slg46110. thi s highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single in tegrated circuit. the macrocells in the device include the following: ? two analog comparators (acmp) ? voltage references (vref) ? four combinatorial look up tables (luts) ? two 2-bit luts ? two 3-bit luts ? seven combination function macrocell ? two selectable dff/ latch or 2-bit luts ? two selectable dff/ latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? pipe delay C 8 stage / 2 output ? one selectable counter /delay or 4-bit lut ? one programmable delay / deglitch filter ? three counter / delay generators (cnt/dly) ? three 8-bit counter/delays with external clock/reset ? four d flip-flop / lat ches (dff) (part of combination function macrocell) ? pipe delay C 8 stage/2 output ( part of combination function ma crocell) ? one bandgap ? rc oscillator (rc osc) ? power on reset (por)
000-0046110-106 page 2 of 81 slg46110 2.0 pin description 2.1 functional and pro gramming pin description pin # pin name function programming function 1 vdd power supply power supply 2 gpi general purpose input v pp (programming voltage) 3 gpio general purpose i/o or anal og comparator 0 (+) programming id pin 4 gpio general purpose i/o or analog comparator 0 (-) n/a 5 nc no connect n/a 6 gpio general purpose i/o or anal og comparator 1 (+) with oe n/a 7 gnd ground n/a 8 gpio general purpose i/o programming mode control 9 gpio general purpose i/o programming sdio pin 10 gpio general purpose i/o with oe and vref output programming s rdwb pin 11 nc no connect n/a 12 gpio general purpose i/o or ex ternal clock input programming sc l pin
000-0046110-106 page 3 of 81 slg46110 3.0 user programmability non-volatile memory (nvm) is used to configure the slg46110s c onnection matrix routing and macrocells. the nvm is one-time-programmable (otp). how ever, silegos greenpak develop ment tools can be used to configure the connection matrix and macrocells, without programming the nvm, to allow on-chip e mulation. this configuration will remain active on the device a s long as it remains powered and c an be re-written as needed to f acilitate rapid design changes. when a design is ready for in-circuit testing, the same greenpa k development tools can be used to program the nvm and create samples for small quantity builds. once the nvm is programmed, the device will retain this conf iguration for the duration of i ts lifetime. once the design is finalized, the design file c an be forwarded to silego to integ rate into the produ ction process. figure 1. steps to create a cu stom silego greenpak device product definition customer creates their own design in greenpak designer program engineering samples with greenpak development tools customer verifies greenpak in system design e-mail design file to greenpak@silego.com e-mail product idea, definition, drawing, or schematic to greenpak@silego.com silego applications engineers will review design specifications with customer samples and design & characterization report sent to customer customer verifies greenpak design custom greenpak part enters production greenpak design approved in system test greenpak design approved greenpak design approved emulate design to verify behavior
000-0046110-106 page 4 of 81 slg46110 4.0 ordering information part number type SLG46110V 12-pin stqfn SLG46110Vtr 12-pin stqfn - tape and reel (3k units)
000-0046110-106 page 5 of 81 slg46110 5.0 electrical specifications 5.1 absolute maximum conditions 5.2 electrical charac teristics (1.8v 5% v dd ) parameter min. max. unit supply voltage on vdd relative to gnd -0.5 7 v dc input voltage g nd - 0.5 vdd + 0.5 v maximum average or dc current (through pin) push-pull 1x -- 12 ma push-pull 2x -- 17 od 1x -- 18 od 2x -- 28 current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 1000 -- v moisture sensitivity level 1 symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 1.80 1.89 v i q quiescent current static inputs and outputs (when acmp, vref and osc are powered down and non-operational) -- 0.5 -- ? a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v air analog input voltage range positive input 0 -- v dd v negative input 0 -- 1.1 v v ih high-level input voltage logic input 1.100 -- v dd v logic input with schm itt trigger 1.270 -- v dd v low-level logic input 0.980 -- v dd v v il low-level input voltage logic input -- -- 0.690 v logic input with schm itt trigger -- -- 0.440 v low-level logic input -- -- 0.520 v i ih high-level input current logic input pins; v in = 1.8 v -1.0 -- 1.0 ? a i il low-level input current logic input pins; v in = 0 v -1.0 -- 1.0 ? a v oh high-level output voltage push-pull 1x, open drain pmos 1x, i oh = 100 ? a 1.680 1.790 -- v push-pull 2x, open drain pmos 2x, i oh = 100 ? a 1.702 1.800 -- v
000-0046110-106 page 6 of 81 slg46110 v ol low-level output voltage push-pull 1x, i ol = 100 ? a -- 0.020 0.030 v push-pull 2x, i ol = 100 ? a -- 0.010 0.020 v open drain nmos 1x, i ol = 100 ? a -- 0.010 0.020 v open drain nmos 2x, i ol = 100 ? a -- 0.010 0.010 v i oh high-level output current (see note 1) push-pull 1x, open drain pmos 1x, v oh = v dd - 0.2 1.040 1.400 -- ma push-pull 2x, open drain pmos 2x, v oh = v dd - 0.2 2.150 2.710 -- ma i ol low-level output current (see note 1) push-pull 1x, v ol = 0.15 v 0.760 1.340 -- ma push-pull 2x, v ol = 0.15 v 1.520 2.660 -- ma open drain nmos 1x, v ol = 0.15 v 1.530 2.670 -- ma open drain nmos 2x, v ol = 0.15 v 3.060 5.130 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma t su startup time from vdd rising past 1.35 v -- 0.27 -- ms pon thr power on threshold v dd level required to start up the chip 1.182 1.346 1.505 v poff thr power off threshold v dd level required to switch off the chip 0.752 0.918 1.110 v note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. symbol parameter condition/note min. typ. max. unit
000-0046110-106 page 7 of 81 slg46110 5.3 electrical charac teristics (3.3v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v i q quiescent current static inputs and outputs (when acmp, vref and osc are powered down and non-operational) -- 0.75 -- ? a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v air analog input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage logic input 1.780 -- v dd v logic input with schm itt trigger 2.130 -- v dd v low-level logic input 1.130 -- v dd v v il low-level input voltage logic input -- -- 1.210 v logic input with schm itt trigger -- -- 0.950 v low-level logic input -- -- 0.690 v i ih high-level input current logic input pins; v in = 3.3 v -1.0 -- 1.0 ? a i il low-level input current logic input pins; v in = 0 v -1.0 -- 1.0 ? a v oh high-level output voltage push-pull 1x,open drain pmos 1x, i oh = 3 ma 2.710 3.090 -- v push-pull 2x, open drain pmos 2x, i oh = 3 ma 2.870 3.190 -- v v ol low-level output voltage push-pull 1x, i ol = 3 ma -- 0.180 0.280 v push-pull 2x, i ol = 3 ma -- 0.090 0.130 v open drain nmos 1x, i ol = 3 ma -- 0.090 0.130 v open drain nmos 2x, i ol = 3 ma -- 0.050 0.070 v i oh high-level output current (see note 1) push-pull 1x, open drain pmos 1x, v oh = 2.4 v 5.830 10.180 -- ma push-pull 2x, open drain pmos 2x, v oh = 2.4 v 11.264 19.660 -- ma i ol low-level output current (see note 1) push-pull 1x, v ol = 0.4 v 4.060 6.440 -- ma push-pull 2x, v ol = 0.4 v 8.130 12.360 -- ma open drain nmos 1x, v ol = 0.4 v 8.130 12.410 -- ma open drain nmos 2x, v ol = 0.4 v 16.260 22.900 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma
000-0046110-106 page 8 of 81 slg46110 5.4 electrical charac teristics (5v 10% v dd ) t su startup time from vdd rising past 1.35 v -- 0.27 -- ms pon thr power on threshold v dd level required to start up the chip 1.182 1.346 1.505 v poff thr power off threshold v dd level required to switch off the chip 0.752 0.918 1.110 v note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. symbol parameter condition/note min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v i q quiescent current static inputs and outputs (when acmp, vref and osc are powered down and non-operational) -- 1.0 -- ? a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v air analog input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage logic input 2.640 -- v dd v logic input with schm itt trigger 3.160 -- v dd v low-level logic input 1.230 -- v dd v v il low-level input voltage logic input -- -- 1.840 v logic input with schm itt trigger -- -- 1.510 v low-level logic input -- -- 0.780 v i ih high-level input current logic input pins; v in = 5 v -1.0 -- 1.0 ? a i il low-level input current logic input pins; v in = 0 v -1.0 -- 1.0 ? a v oh high-level output voltage push-pull 1x,open drain pmos 1x, i oh = 5 ma 4.150 4.730 -- v push-pull 2x, open drain pmos 2x, i oh = 5 ma 4.300 4.860 -- v v ol low-level output voltage push-pull 1x, i ol = 5 ma -- 0.230 0.330 v push-pull 2x, i ol = 5 ma -- 0.120 0.160 v open drain nmos 1x, i ol = 5 ma -- 0.120 0.160 v open drain nmos 2x, i ol = 5 ma -- 0.070 0.090 v i oh high-level output current (see note 1) push-pull 1x, open drain pmos 1x, v oh = 2.4 v 21.808 29.100 -- ma push-pull 2x, open drain pmos 2x, v oh = 2.4 v 40.598 56.080 -- ma symbol parameter condition/note min. typ. max. unit
000-0046110-106 page 9 of 81 slg46110 i ol low-level output current (see note 1) push-pull 1x, v ol = 0.4 v 6.010 9.730 -- ma push-pull 2x, v ol = 0.4 v 11.590 19.460 -- ma open drain nmos 1x, v ol = 0.4 v 11.760 19.460 -- ma open drain nmos 2x, v ol = 0.4 v 19.120 35.621 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma t su startup time from vdd rising past 1.35 v -- 0.27 -- ms pon thr power on threshold v dd level required to start up the chip 1.182 1.346 1.505 v poff thr power off threshold v dd level required to switch off the chip 0.752 0.918 1.110 v note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. symbol parameter condition/note min. typ. max. unit
000-0046110-106 page 10 of 81 slg46110 5.5 idd estimator 5.6 timing estimator table 1. typical current est imated for each macrocell. symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit i current chip quiescent 0.5 0.8 1.0 ? a vref 56.9 56.9 63.3 ? a vref buffer (each) 2.7 13.0 13.7 ? a osc 25 khz, predivide = 1 3.1 4.8 6.4 ? a osc 25 khz, predivide = 8 3.0 4.5 6.0 ? a osc 2 mhz, predivide = 1 27.4 45.4 67.4 ? a osc 2 mhz, predivide = 8 17.5 23.7 29.5 ? a 1st acmp used (includes vref) 60.6 62.0 68.4 ? a each additional acmp add 3.7 4.9 5.1 ? a table 2. typical delay estimated for each macrocell. symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit rising falling rising falling rising falling tpd delay digital input without schmitt trigger - push pull 35.3 34.4 14.5 14.3 10.3 10.5 ns tpd delay digital input with schmitt trigger - push pull 34.8 32.9 14.2 13.8 10.0 10.1 ns tpd delay low voltage digital inpu t - push pull 37.8 450.0 15.0 208.2 10.5 142.3 ns tpd delay digital input without schmitt trigger -- nmos 73.5 26.0 16.3 ns tpd delay output enable from pin , oe hi-z to 1 44.6 17.9 12.4 ns tpd delay output enable from pin , oe hi-z to 0 43.0 17.6 12.5 ns tpd delay 2-bit lut (latch shared macrocell inputs) 29.6 24.8 11.5 10.1 8.2 6.9 ns tpd delay latch (2-bit lut shared macrocell inputs) 29.2 31.5 11.8 12.5 8.4 8.4 ns tpd delay 3-bit lut (latch shared macrocell inputs) 33.0 27.4 12.8 11.1 9.1 7.5 ns tpd delay latch with nrst/nset (3-bit lut shared macrocell inputs) 29.9 32.4 12.1 13.0 8.7 8.7 ns tpd delay 4-bit lut (shared macroc ell inputs) 29.2 27.2 11.2 10.8 8.0 7 .3 ns tpd delay 2-bit lut 19.4 18.8 7.2 7.4 5.1 5.0 ns tpd delay 3-bit lut 22.3 22.7 8.3 8.9 6.0 5.9 ns tpd delay cnt/dly 38.4 36.0 15.2 15.1 10.8 10.4 ns tpd delay cnt/dly (shared macroce ll inputs) 41.0 36.2 1 6.3 15.6 11.5 10 .9 ns tpd delay cnt3/dly3 rising edge detect (shared macrocell inputs) 39.7 15.7 11.1 ns tpd delay cnt3/dly3 falling edge detect (shared macrocell inputs) 41.5 16.9 11.6 ns tpd delay cnt3/dly3 both edge detect (shared macrocell inputs) 39.7 41.5 15.7 16.9 11.1 11.6 ns tpd delay filter 183.1 186.2 73.5 75.7 47.9 50.2 ns
000-0046110-106 page 11 of 81 slg46110 5.7 typical counter/de lay offset measurements 5.8 expected delays and widths table 3. typical counter/de lay offset measurements. parameter rc osc freq rc osc power v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit offset 25khz auto 19 14 12 ? s offset 2mhz auto 7 4 4 ? s frequency settling time 25khz auto 19 14 12 ? s frequency settling time 2mhz auto 14 14 14 ? s variable (clk period) 25khz forced 0-40 0-40 0-40 ? s variable (clk period) 2mhz forced 0-0.5 0-0.5 0-0.5 ? s tpd (non-delayed edge) 25khz/2mhz either 35 14 10 ns table 4. expected delays and wid ths for programmable delay (typi cal). symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit time1 width, 1 cell pdly mode:(any)edge detect, edge detect output 272.4 128.8 97.5 ns time1 width, 2 cell pdly mode:(any)edge detect, edge detect output 582.7 272.6 205.1 ns time1 width, 3 cell pdly mode:(any)edge detect, edge detect output 893.4 416.6 312.9 ns time1 width, 4 cell pdly mode:(any)edge detect, edge detect output 1203.4 560.6 420.9 ns time2 delay, 1 cell pdly mode:(any)edge detect, edge detect output 39.3 15.7 10.9 ns time2 delay, 2 cell pdly mode:(any)edge detect, edge detect output 39.3 15.7 10.9 ns time2 delay, 3 cell pdly mode:(any)edge detect, edge detect output 39.3 15.7 10.9 ns time2 delay, 4 cell pdly mode:(any)edge detect, edge detect output 39.3 15.7 10.9 ns time1 delay, 1 cell pdly mode: both edge delay (shared macrocell inputs) 354 161.5 120.1 ns time1 delay, 2 cell pdly mode: both edge delay (shared macrocell inputs) 664.2 305.2 227.8 ns time1 delay, 3 cell pdly mode: both edge delay (shared macrocell inputs) 974.9 449.1 335.7 ns time1 delay, 4 cell pdly mode: both edge delay (shared macrocell inputs) 1284.8 593.1 443.6 ns time1 width cnt3/dly3 rising edge detect (shared macrocell inputs) 63.6 32.4 22.9 ns time1 width cnt3/dly3 falling edge detect (shared macrocell inputs) 61.3 31.1 22.5 ns time1 width cnt3/dly3 both edge detect (shared macrocell inputs) 62.2 31.6 22.7 ns
000-0046110-106 page 12 of 81 slg46110 5.9 typical pulse width performance table 5. typical pulse width performance. parameter v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit filtered pulse width < 150 < 55 < 35 ns
000-0046110-106 page 13 of 81 slg46110 6.0 summary of macrocell function 6.1 i/o pins ? digital input (low voltage or normal voltage, with or without schmitt trigger) ? open drain outputs ? push pull outputs ? analog i/o ? 10 k ? /100 k ? /1 m ?? pull-up/pull-down resistors 6.2 connection matrix ? digital matrix for circuit co nnections based on user design 6.3 analog compa rators (2 total) ? selectable hysteresis 0 mv/25 mv/50 mv/200 mv 6.4 voltage reference ? used for references on analog comparators ? can also be driven to external pin (pin 10) 6.5 combinational logic look up tables (luts C 4 total) ? two 2-bit lookup tables ? two 3-bit lookup tables 6.6 combination functi on macrocells (7 total) ? two selectable dff/latch or 2-bit luts ? two selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable cnt/dly or 4-bit lut ? one programmable delay or deglitch filter 6.7 delays/counters (3 total) ? three 8-bit delays/counters with external clock/reset: range 1 -255 clock cycles 6.8 pipe delay (part of combination function macrocell) ? 8 stage / 2 output ? two 1-8 stage sel ectable outputs. 6.9 programmable delay ? 125 ns/250 ns/375 ns/500 ns @ 3.3 v ? includes edge detection function 6.10 additional logic functions (part of combination function macrocell) ? one deglitch filter macrocell
000-0046110-106 page 14 of 81 slg46110 6.11 rc oscillator ? 25 khz and 2 mhz s electable frequency ? first stage clock pre=divider (4) : osc/1, osc/2, osc/4, and os c/8 ? second stage divider control wit h two outputs, out0 and out1 ( 8): selectable (osc/1, osc /2, osc/3, osc/4, osc/8, osc/12, osc/24, or osc/64) 6.12 power on reset (por)
000-0046110-106 page 15 of 81 slg46110 7.0 i/o pins the slg46110 has a total of 8 multi-function i/o pins which can function as either a user defin ed input or output, as well as serving as a special function (s uch as outputting the voltage r eference), or serving as a signal for programming of the on-chi p non volatile memory (nvm). normal mode pin definitions are as follows: ? pin 1: v dd power supply ? pin 2: general purpose input ? pin 3: general purpose i/o or analog comparator 0 (+) ? pin 4: general purpose i/o or analog comparator 0 (-) ? pin 5: no connect ? pin 6: general purpose i/o or analog comparator 1 (+) with oe ? pin 7: ground ? pin 8: general purpose i/o ? pin 9: general purpose i/o ? pin 10: general purpose i/o with oe and vref output ? pin 11: no connect ? pin 12: general purpose i /o or external clock input programming mode pin definitions are as follows: ? pin 1: v dd power supply ? pin 2: v pp programming voltage ? pin 3: programming id pin ? pin 7: ground ? pin 8: programming mode control ? pin 9: programming sdio pin ? pin 10: programming srdwb pin ? pin 12: programming scl pin of the 8 user defined i/o pins on the slg46110, all but one of the pins (pin 2) can serve as both digital input and digital ou tput. pin 2 can only serve as a digital input pin. 7.1 input modes each i/o pin can be configured as a digital input pin with/with out buffered schmitt trigger, or can also be configured as a lo w voltage digital input. pins 3, 4, and 6 can als o be configured to serve as analog inputs to the on-chip comparators. 7.2 output modes pins 3, 4, 6, 8, 9, 10, and 12 ca n all be configured as digital output pins. 7.3 pull up/down resistors all i/o pins have the option for user selectable resistors conn ected to the input structure. th e selectable values on these re sistors are 10 k ? , 100 k ? and 1 m ? . in the case of pin 2, the resistors are fixed to a pull-down configuration. in the case of all other i/o pins, the internal resistors can be configured as either pull-u p or pull-downs.
000-0046110-106 page 16 of 81 slg46110 7.4 i/o register settings 7.4.1 pin 2 re gister settings 7.4.2 pin 3 re gister settings table 6. pin 2 re gister settings signal function register bit address register definition pin 2 mode control reg <380:379> 00 : digital input without schmit t trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved pin 2 pull down resistor value selection reg <382:381> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor table 7. pin 3 re gister settings signal function register bit address register definition pin 3 mode control reg <385:383> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain nmos pin 3 pull up/down resistor value selection reg <387:386> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 3 pull up/down resistor selection reg <388> 0: pull down resistor 1: pull up resistor pin3 driver strength selection reg <389> 0: 1x 1: 2x
000-0046110-106 page 17 of 81 slg46110 7.4.3 pin 4 re gister settings 7.4.4 pin 6 re gister settings table 8. pin 4 re gister settings signal function register bit address register definition pin 4 mode control reg <392:390> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain nmos pin 4 pull up/down resistor value selection reg <394:393> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 4 pull up/down resistor selection reg <395> 0: pull down resistor 1: pull up resistor pin 4 driver strength selection reg <396> 0: 1x 1: 2x table 9. pin 6 re gister settings signal function register bit address register definition pin 6 mode control (sig_pin6_oe=0) reg <398:397> 00: digital i nput without schmitt trigger 01: digital input with schmitt trigger 11: low voltage digital input 10: analog input pin 6 mode control (sig_pin6_oe =1) reg <400:399> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x pin 6 pull up/down resistor value selection reg <402:401> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 6 pull up/down resistor selection reg <403> 0: pull down resistor 1: pull up resistor
000-0046110-106 page 18 of 81 slg46110 7.4.5 pin 8 re gister settings 7.4.6 pin 9 re gister settings table 10. pin 8 register settings signal function register bit address register definition pin 8 mode control reg <406:404> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain nmos pin 8 pull up/down resistor value selection reg <408:407> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 8 pull up/down resistor selection reg <409> 0: pull down resistor 1: pull up resistor pin 8 driver strength selection reg <410> 0: 1x 1: 2x table 11. pin 9 register settings signal function register bit address register definition pin 9 mode control reg <413:411> 000: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain nmos pin 9 pull up/down resistor value selection reg <415:414> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 9 pull up/down resistor selection reg <416> 0: pull down resistor 1: pull up resistor pin 8 driver strength selection reg <417> 0: 1x 1: 2x
000-0046110-106 page 19 of 81 slg46110 7.4.7 pin 10 register settings 7.4.8 pin 12 register settings table 12. pin 10 register settings signal function register bit address register definition pin 10 mode control (sig_pin10_oe =0) reg <419:418> 00: digital i nput without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input / output pin 10 mode control (sig_pin10_oe =1) reg <419:418> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x pin 10 pull up/down resistor value selection reg <423:422> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 10 pull up/down resistor selection reg <424> 0: pull down resistor 1: pull up resistor table 13. pin 12 register settings signal function register bit address register definition pin 12 mode control reg <427:425> 000: digital inp ut without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain nmos pin 12 pull up/down resistor value selection reg <429:428> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 12 pull up/down resistor selection reg <430> 0: pull down resistor 1: pull up resistor pin 12 driver strength selection reg <431> 0: 1x 1: 2x
000-0046110-106 page 20 of 81 slg46110 7.5 gpi io structure 7.5.1 gpi io structure (for pin 2) figure 2. pin 2 gpi io structure diagram pad digital in s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schmitt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: reserved
000-0046110-106 page 21 of 81 slg46110 7.6 matrix oe io structure 7.6.1 matrix oe io struc ture (for pin 6, 10) figure 3. matrix oe io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schm itt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1 analog io digital out digital out oe od2x_en oe od1x_en digital out oe pp2x_en digital out oe pp1x_en
000-0046110-106 page 22 of 81 slg46110 7.7 register oe io structure 7.7.1 register oe io structu re (for pins 3, 4, 8, 9, 12) figure 4. register oe io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1 001: digital in with schmitt trigger, smt_en=1 010: low voltage digital in mode, lv_en = 1 011: analog io mode 100: push-pull mode, pp_en=1 101: nmos open drain mode, odn_en=1 110: pmos open drain mode, odp_en=1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 analog io digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en 2x_en odp_en
000-0046110-106 page 23 of 81 slg46110 8.0 connection matrix the connection matrix in the slg46110 is used to create the int ernal routing for internal functions of the device once it is programmed. the registers are pr ogrammed from the one-time nvm cell during test mode operation. all of the connection point for each logic cell within the slg46110 has a specific digital bit code assigned to it that is either set to active high or inactive low based on the design that i s created. once the 512 registe r bits within the slg46110 are p rogrammed a fully custom circui t will be created. the connection matrix has 32 inpu ts and 44 outputs. each of the 32 inputs to the connection matrix is hard-wired to a particul ar source macrocell, including i/o pins, luts, analog comparators, other digital resources and v dd and v ss . the input to a digital macrocell uses a 5-bit register to select one of these 32 input lines. for a complete list of the slg461 10s register table, see secti on 16.0 appendix a - slg46110 register definition . figure 5. connection matrix figure 6. connection matrix example vss 0 pin 2 digital in 1 pin 3 digital in 2 pin 4 digital in 3 matrix input signal functions n pin12 digital in 30 vdd 31 n function registers 43 pin12 digital output source reg <219:215> 0 pin3 digital output source reg <4:0> 1 pin4digital output source reg <9:5> 2 pin6 digital output source reg <14:10> matrix inputs matrix outputs pin 2 pin 3 pin 10 connection matrix lut pin 3 pin 2 lut pin 10 function
000-0046110-106 page 24 of 81 slg46110 8.1 matrix input table table 14. matrix input table n matrix input signal function matrix decode 4 3 2 1 0 0 vss 00000 1 pin2 digital input 0 0 0 0 1 2 pin3 digital input 0 0 0 1 0 3 pin4 digital input 0 0 0 1 1 4 pin6 digital input 0 0 1 0 0 5 lut2_0 output (dff/latch_0 output) 0 0 1 0 1 6 lut2_1 output (dff/latch_1 output) 0 0 1 1 0 7 lut2_2 output 0 0 1 1 1 8 lut2_3 output 0 1 0 0 0 9 lut3_0 output (dff/latch_2 out put with resetb or seb) 0 1 0 0 1 10 lut3_1 output (dff/latch_3 output with resetb or seb) 0 1 0 1 0 11 lut3_2 output 0 1 0 1 1 12 lut3_3 output 0 1 1 0 0 13 lut3_4 output(pipe delay ouput0) 0 1 1 0 1 14 pipe delay ouput1 0 1 1 1 0 15 lut4_0 output (cnt_dly2 output (8 bit w/ ext ck,reset)) 0 1 1 1 1 16 cnt_dly0 output (8 bit w/ ext c k (shared bottom delay/cnt),re set)10000 17 cnt_dly1 output (8 bit w/ ext c k (from dedicat ed matrix out- put),reset) 10001 18 cnt_dly3 (8 bit) output 1 0 0 1 0 19 acmp_0 output 10011 20 acmp_1 output 10100 21 edge detect output 1 0 1 0 1 22 programmable delay with edge detector output (deglitch filter o ut- put) 10110 23 internal oscillator output1 (one of /1,/2,/3,/4,/8,12/,24/,64/ selected by reg) 10111 24 internal oscillator output2 (one of /1,/2,/3,/4,/8,12/,24/,64/ selected by reg) 11000 25 bandgap ok signal 1 1 0 0 1 26 por output to matrix 1 1 0 1 0 27 pin8 digital input 1 1 0 1 1 28 pin9 digital input 1 1 1 0 0 29 pin10 digital input 1 1 1 0 1 30 pin12 digital input 1 1 1 1 0 31 vdd 11111
000-0046110-106 page 25 of 81 slg46110 8.2 matrix output table table 15. matrix output table register bit address matrix output signal function matrix output number reg <4:0> pin 3 digital out source 0 reg <9:5> pin 4 digital out source 1 reg <14:10> pin 6 digital out source 2 reg <19:15> pin 6 output enable 3 reg <24:20> in0 of lut2 _0 (clock input of dff0) 4 reg <29:25> in1 of lut2_0 (data input of dff0) 5 reg <34:30> in0 of lut2 _1 (clock input of dff1) 6 reg <39:35> in1 of lut2_1 (data input of dff1) 7 reg <44:40> in0 of lut2_2 8 reg <49:45> in1 of lut2_2 9 reg <54:50> in0 of lut2_3 10 reg <59:55> in1 of lut2_3 11 reg <64:60> in0 of lut3_0 (clock input of dff2 with nreset/nset) 12 reg <69:65> in1 of lut3 _0 (data input of dff 2 with nreset/nset) 1 3 reg <74:70> in2 of lut3_0 (resetb or setb of dff2 with nreset/ns et) 14 reg <79:75> in0 of lut3_1 (clock input of dff3 with nreset/nset) 15 reg <84:80> in1 of lut3 _1 (data input of dff 3 with nreset/nset) 1 6 reg <89:85> in2 of lut3_1 (resetb or setb of dff3 with nreset/ns et) 17 reg <94:90> in0 of lut3_2 18 reg <99:95> in1 of lut3_2 19 reg <104:100> in2 of lut3_2 20 reg <109:105> in0 of lut3_3 21 reg <114:110> in1 of lut3_3 22 reg <119:115> in2 of lut3_3 23 reg <124:120> in0 of lut3_4 (input of pipe delay) 24 reg <129:125> in1 of lut3_4 (resetb of pipe delay) 25 reg <134:130> in2 of lut3_ 4 (clock of pipe delay) 26 reg <139:135> in0 of l ut4_0 (input for del ay2 ext. clock or coun ter2 external clock) 27 reg <144:140> in1 of lut 4_0 (input for delay 2 or counter2 reset input) 28 reg <149:145> in2 of lut4_0 29 reg <154:150> in3 of lut4_0 30 reg <159:155> input for dela y0 or counter0 reset input 31 reg <164:160> input for dela y1 or counter1 reset input 32 reg <169:165> input for delay0/1 e xt. clock or counter1 external clock 33 reg <174:170> input for dela y3 or counter3 reset input 34 reg <179:175> pdb for acmp0 35 reg <184:180> pdb for acmp1 36 reg <189:185> input for programm able delay(deglit ch filter input )37
000-0046110-106 page 26 of 81 slg46110 reg <194:190> power down for osc. ( higher priority) (high = powe r down). 38 reg <199:195> pin 8 di gital out source 39 reg <204:200> pin 9 digital out source 40 reg <209:205> pin 10 digital out source 41 reg <214:210> pin 10 output enable 42 reg <219:215> pin 12 digital out source 43 table 15. matrix output table register bit address matrix output signal function matrix output number
000-0046110-106 page 27 of 81 slg46110 9.0 combinatorial logic combinatorial logic is supported via four lookup tables (luts) within the slg46110. there are two 2-bit luts and two 3-bit lut s. the device also includes six combination function macrocells th at can be used as luts. for more details, please see section 10.0 combination function macrocells. inputs/outputs for the four lut s are configured from the connec tion matrix with specific logic functions being defined by the state of nvm bits. the outputs of the luts can be configured to any u ser defined function, including the following standard digital logic devices (and, nand, or, nor, xor, xnor). 9.1 2-bit lut the two 2-bit luts each take in two input signals from the conn ection matrix and produce a sing le output, which goes back into the connection matrix. .. each 2-bit lut uses a 4-bit regi ster signal to define their out put functions; 2-bit lut2 is defined by reg <235:232> 2-bit lut3 is defined by reg <239:236> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the t wo 2-bit lut logic cells. figure 7. 2-bit luts table 18. 2-bit lut stand ard digital functions. function msb lsb and-2 1000 nand-2 0 1 1 1 or-2 1110 nor-2 0 0 0 1 xor-2 0110 xnor-2 1001 2-bit lut2 out in1 in0 reg <235:232> from connection matrix output <8> from connection matrix output <9> to connection matrix input <7> 2-bit lut3 out in1 in0 reg <239:236> from connection matrix output <10> from connection matrix output <11> to connection matrix input <8> table 16. 2-bit lut2 truth table. in1 in0 out 0 0 reg <232> 0 1 reg <233> 1 0 reg <234> 1 1 reg <235> table 17. 2-bit lut3 truth table. in1 in0 out 0 0 reg <236> 0 1 reg <237> 1 0 reg <238> 1 1 reg <239>
000-0046110-106 page 28 of 81 slg46110 9.2 3-bit lut the two 3-bit luts each take in three input signals from the co nnection matrix and produce a single output, which goes back in to the connection matrix. each 3-bit lut uses a 8-bit regi ster signal to define their out put functions; 3-bit lut2 is defined by reg <265:258> 3-bit lut3 is defined by reg <273:266> figure 8. 3-bit luts 3-bit lut2 out in1 in0 reg <265:258> from connection matrix output <18> from connection matrix output <19> to connection matrix input <11> 3-bit lut3 out in1 in0 reg <273:266> from connection matrix output <21> from connection matrix output <22> to connection matrix input <12> in2 from connection matrix output <20> in2 from connection matrix output <23> table 19. 3-bit lut2 truth table. in2 in1 in0 out 0 0 0 reg <258> 0 0 1 reg <259> 0 1 0 reg <260> 0 1 1 reg <261> 1 0 0 reg <262> 1 0 1 reg <263> 1 1 0 reg <264> 1 1 1 reg <265> table 20. 3-bit lut3 truth table. in2 in1 in0 out 0 0 0 reg <266> 0 0 1 reg <267> 0 1 0 reg <268> 0 1 1 reg <269> 1 0 0 reg <270> 1 0 1 reg <271> 1 1 0 reg <272> 1 1 1 reg <273>
000-0046110-106 page 29 of 81 slg46110 the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the t wo 3-bit lut logic cells. table 21. 3-bit lut stand ard digital functions. function msb lsb and-3 10000000 nand-3 01111111 or-3 11111110 nor-3 00000001 xor-3 10010110 xnor-3 01101001
000-0046110-106 page 30 of 81 slg46110 10.0 combination function macrocells the slg46110 has seven combinat ion function macrocells that can serve more than one logic or t iming function. i n six of these cases, they can serve as a look up table (lut), or as another l ogic or timing function. in the last case, it can serve as eith er a programmable delay or deglitch f ilter. see the list below for t he functions that can be implemented in these macrocells; ? two macrocells that can serve as either 2-bit luts or as d fli p flops. ? two macrocells that can serve as either 3-bit luts or as d fli p flops. ? one macrocell that can serve as either 3-bit lut or as pipe de lay ? one macrocells that can serve as either 4-bit luts or as 8-bit counter / delays ? one macrocell that can serve as either a progra mmable delay or as a deglitch filter inputs/outputs for the seven com bination function macrocells ar e configured from the connection matrix with specific logic fun c- tions being defined by the state of nvm bits. when used as a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, including th e following standard digital logic device s (and, nand, or, nor, xor, xnor). when used as a d flip flop / latch, the source and destination of the inputs and outputs for th e dff/latches are configured fr om the connection matrix. all dff/la tch macrocells have user selec tion for initial state, and all h ave the option to connect both the q and q bar outputs to the connection matrix. the macrocells df f2, dff3 have an additional input from the matrix that can serve as a nset or nreset f unction to the macrocell. the operation of the d flip-flop and latch will follow the func tional descriptions below: dff: clk is rising edge triggered , then q = d; otherwise q will not change latch: if clk = 0, then q = d 10.1 2-bit lut or d flip flop macrocells there are two macrocells that can serve as either 2-bit luts or as d flip flops. when used to implement lut functions, the 2-b it luts each take in two input signals from the connection matrix and produce a single output, which goes back into the connectio n matrix. when used to implement d flip flop function, the two in put signals from the connection matrix go to the data (d) and c lock (clk) inputs for the flip flop, with the outpu t going back to t he connection matrix.
000-0046110-106 page 31 of 81 slg46110 figure 9. 2-bit lut0 or dff0 figure 10. 2-bit lut1 or dff1 dff0 clk d 2-bit lut0 out in0 in1 to connection matrix input <5> 4-bits nvm from connection matrix output <5> 1-bit nvm reg <227:224> reg <240> from connection matrix output <4> q/nq reg <225> output select (q or nq) dff1 2-bit lut1 from connection matrix output <7> reg <231:228> reg <241> from connection matrix output <6> to connection matrix input <6> clk d out in0 in1 4-bits nvm 1-bit nvm q/nq reg <229> output select (q or nq)
000-0046110-106 page 32 of 81 slg46110 10.1.1 2-bit lut or d flip flop macrocells used as 2-bit luts each macrocell, when programmed for a lut function, uses a 4-bi t register to define their output function: 2-bit lut0 is defined by reg <227:224> 2-bit lut1 is defined by reg <231:228> 10.1.2 2-bit lut or d flip flop macrocells used as d flip flo p register settings table 24. dff0 register settings signal function register bit address register definition dff0 or latch select reg <224> 0: dff function 1: latch function dff0 output select reg <225> 0: q output 1: nq output dff0 initial polarity select reg <226> 0: low 1: high lut2_0 data reg < 235:232> lut2_0 data lut2_0 or dff0 select reg <240> 0: lut2_0 1: dff0 table 25. dff1register settings signal function register bit address register definition dff1 or latch select reg <228> 0: dff function 1: latch function dff1 output select reg <229> 0: q output 1: nq output dff1 initial polarity select reg <230> 0: low 1: high lut2_1 data reg < 239:236> lut2_1 data lut2_1 or dff1 select reg <241> 0: lut2_1 1: dff1 table 22. 2-bit lut0 truth table. in1 in0 out 0 0 reg <224> 0 1 reg <225> 1 0 reg <226> 1 1 reg <227> table 23. 2-bit lut1 truth table. in1 in0 out 0 0 reg <228> 0 1 reg <229> 1 0 reg <230> 1 1 reg <231>
000-0046110-106 page 33 of 81 slg46110 10.2 3-bit lut or d flip flop with set/reset macrocells there are two macrocells that can serve as either 3-bit luts or as d flip flops. when used to implement lut functions, the 3-b it luts each take in three input signals from the connection matri x and produce a single output, which goes back into the connect ion matrix. when used to implement d flip flop function, the three input signals from the connection matrix go to the data (d) and clock (clk) and set/ reset (rrst/nset) inputs for the flip flop, with the outpu t going back to the con nection matrix.. figure 11. 3-bit lut0 or dff2 figure 12. 3-bit lut1 or dff3 dff2 clk d to connection matrix< input 9> 8-bits nvm from connection matrix output <14> 1-bit nvm 3-bit lut0 out in1 in2 in0 nrst/nset from connection matrix output <13> from connection matrix output <12> reg <249:242> reg <282> q/nq reg <243> output select (q or nq) dff3 clk d 8-bits nvm 1-bit nvm 3-bit lut1 out in1 in2 in0 nrst/nset from connection matrix output <17> from connection matrix output <16> from connection matrix output <15> reg <257:250> reg <283> to connection matrix< input 10> q/nq reg <251> output select (q or nq)
000-0046110-106 page 34 of 81 slg46110 10.2.1 3-bit lut or d flip flop macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut2 is defined by reg <249:242> 3-bit lut3 is defined by reg <257:250> table 26. 3-bit lut0 truth table. in2 in1 in0 out 0 0 0 reg <242> 0 0 1 reg <243> 0 1 0 reg <244> 0 1 1 reg <245> 1 0 0 reg <246> 1 0 1 reg <247> 1 1 0 reg <248> 1 1 1 reg <249> table 27. 3-bit lut1 truth table. in2 in1 in0 out 0 0 0 reg <250> 0 0 1 reg <251> 0 1 0 reg <252> 0 1 1 reg <253> 1 0 0 reg <254> 1 0 1 reg <255> 1 1 0 reg <256> 1 1 1 reg <257>
000-0046110-106 page 35 of 81 slg46110 10.2.2 3-bit lut or d flip flop macrocells used as d flip flo p register settings table 28. dff2 register settings signal function register bit address register definition dff2 or latch select reg <242> 0: dff function 1: latch function dff2 output select reg <243> 0: q output 1: nq output dff2 initial polarity select reg <244> 0: low 1: high dff2 rstb/setb select reg <245> 1: setb from matrix out 0: resetb from matrix out lut3_0 data reg < 265:258> lut3_0 data lut3_0 or dff2 select reg <282> 0: lut3_0 1: dff2 table 29. dff3 register settings signal function register bit address register definition dff3 or latch select reg <250> 0: dff function 1: latch function dff3 output select reg <251> 0: q output 1: nq output dff3 rstb/setb select reg <252> 1: setb from matrix out 0: resetb from matrix out dff3 initial polarity select reg <253> 0: low 1: high lut3_1 data reg < 273:266> lut3_1 data lut3_1 or dff3 select reg <283> 0: lut3_1 1: dff3
000-0046110-106 page 36 of 81 slg46110 10.3 3-bit lut or pipe delay macrocell there is one macrocell that can serve as either a 3-bit lut or as a pipe delay. when used to implement lut functions, the 3-bit lut take in thr ee input signals from the connection matrix and produces a sing le output, which goes back in to the connection matrix. when used as an 8-stage pipe delay, there are three inputs sign als from the matrix, input (in), clock (ck) and reset (nreset). the pipe delay cell is built fro m d flip-flop logic cells that provide the three delay options, two of which are user selectab le. the dff cells are tied in series where the output (q) of each delay cell goes to the next dff cell. the two outputs (out0 and out1 ) provide user selectable options for 1 to 8 stages of delay ther e are delay output points for each set of the out0 and out1 out puts to a 3-input mux that is controlled by reg <666:663> for out0 a nd reg <670:667> for out1. the 3-input mux is used to control the selection of t he amount of delay. the overall time of the delay is based on the clock used in the slg46110 design. each dff cell has a time delay of the inverse of the clock time (either externa l clock or the rc oscillator w ithin the slg46110). the sum of the number of dff cells used wi ll be the total time delay of th e pipe delay logic cell. figure 13. 3-bit lut4 or pipe delay 3-bit lut4 out in1 in0 reg <281:274> from connection matrix output <24> from connection matrix output <25> in2 from connection matrix output <26> 8 flip-flops in nreset ck from connection matrix output <25> from connection matrix output <24> from connection matrix output <26> reg <276:274> reg <279:277> to connection matrix input<14> out1 out0 reg <432> 1 0 to connection matrix input<13> reg <284> 0 1
000-0046110-106 page 37 of 81 slg46110 10.3.1 3-bit lut or pipe delay macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut4 is defined by reg <281:274> 10.3.2 3-bit lut or pipe del ay macrocells used as pipe delay register settings table 31. pipe delay register settings signal function register bit address register definition out0 select reg <276:274> data (pipe number) out1 select reg <279:277> data (pipe number) lut3_4 or pipe de- lay output select reg <284> 0: lut3_4 1: pipe delay table 30. 3-bit lut4 truth table. in2 in1 in0 out 0 0 0 reg <274> 0 0 1 reg <275> 0 1 0 reg <276> 0 1 1 reg <277> 1 0 0 reg <278> 1 0 1 reg <279> 1 1 0 reg <280> 1 1 1 reg <281>
000-0046110-106 page 38 of 81 slg46110 10.4 4-bit lut or 8- bit counter / delay macrocells there is one macrocell that can serve as either a 4-bit lut or as a counter / delay. when used to implement lut functions, the 4-bit lut takes in four input signals from the connection matri x and produces a single output, which goes back into the connec tion matrix. when used to implement 8-bit counter / delay function, two of the four input signals from the connection matrix go to the external clock (ext_clk) and reset (dly_n/cnt_reset) for the co unter/delay, with the output going back to the connection matri x. figure 14. 4-bit lut0 or cnt/dly2 cnt/dly2 out clk dly_n/cnt_reset 4-bit lut0 out in0 in1 16-bits nvm 1-bit nvm in2 in3 to connection matrix input <15> from connection matrix output <28> reg <300:285> reg <301> from connection matrix output <27> from connection matrix output <30> from connection matrix output <29>
000-0046110-106 page 39 of 81 slg46110 10.4.1 4-bit lut or 8-bit counter / delay macrocell used as 4 -bit luts each macrocell, when programmed for a lut function, uses a 16-b it register to define their output function: 4-bit lut0 is defined by reg <300:285> table 33. 4-bit lut stand ard digital functions function msb lsb and-4 1000000000000000 nand-40111111111111111 or-4 1111111111111110 nor-4 0000000000000001 xor-4 0110100110010110 xnor-41001011001101001 table 32. 4-bit lut0 truth table. in3 in2 in1 in0 out 0000reg < 285> 0001reg < 286> 0010reg < 287> 0011reg < 288> 0100reg < 289> 0101reg < 290> 0110reg < 291> 0111reg < 292> 1000reg < 293> 1001reg < 294> 1010reg < 295> 1011reg < 296> 1100reg < 297> 1101reg < 298> 1110reg < 299> 1111reg < 300>
000-0046110-106 page 40 of 81 slg46110 10.4.2 4-bit lut or 8-bit counter / delay macrocells used as 8-bit counter / del ay register settings 10.5 programmable delay / edge detector the slg46110 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four timings (time1) configured in the greenpak designer. the progra mmable time delay cell can generate one of four different delay patterns, rising edge detection , falling edge detection, both e dge detection and both edge delay. these four patterns can be f urther modified with the addition of delayed edge detection, which add s an extra unit of delay as well as glitch rejection during the delay period. see the timing diagrams b elow for further information. note : the input signal must be longer than the delay, otherwise it will be filtered out. table 34. cnt/dly2 register settings signal function register bit address register definition counter/delay2 mode selection reg <285> 0: delay mode 1: counter mode counter/delay2 clock source select reg <288:286> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter1 overflow counter/delay2 control data reg <296:289> 1 C 256 (delay time = (counter contro l data +2) /f req) delay2 mode select or asynchronous counter reset reg <298:297> 00: delay on both f alling and risi ng edges(for del ay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode lut4_0 or count- er2 select reg <301> 0: lut4_0 1: counter2 figure 15. programmable delay programmable delay out in reg <489:488> from connection matrix output <37> to connection matrix input <22> reg <487:486> edge mode selection delay value selection 1 0 reg <485> deglitch filter out 1 0 reg <485> deglitch filter in
000-0046110-106 page 41 of 81 slg46110 10.6 programmable delay timing diagram - edge detector output note: for delays and widths refer to table 4 . 10.6.1 programmable de lay register settings figure 16. edge detector output figure 17. delayed edge detector output table 35. programmable de lay register settings signal function register bit address register definition programmable delay or filter output select reg <485> 0: programmable delay output 1: filter output select the edge mode of programmable delay & edge detector reg <487:486> 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay time1 edge detector output in rising edge detector falling edge detector both edge detector both edge delay time1 time1 can be set by register delayed edge detector output delayed rising edge detector delayed falling edge detector delayed both edge detector delayed both edge delay time2 time2 time1 can be set by register time2 is a fixed value in time1 time1
000-0046110-106 page 42 of 81 slg46110 delay value select for programmable delay & edge detector (vdd = 3.3v, typical condition) reg <489:488> 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns table 35. programmable de lay register settings signal function register bit address register definition
000-0046110-106 page 43 of 81 slg46110 10.7 deglitch filter the slg46110 has an additional logic function that is connected directly to the connection matrix inputs and outputs. there is one deglitch filter. figure 18. deglitch filter deglich filter in deglitch filter out filter reg <441> c r
000-0046110-106 page 44 of 81 slg46110 11.0 analog comparators (acmp) there are two analog comparator ( acmp) macrocells in the slg461 10. in order for the acmp cells to be used in a greenpak design, the power up signals (acmp0_pdb and acmp1_pdb) need to be active. by connecting to signals coming from the connection matrix, it is possible to have each acmp be on conti nuously, off continuously, or switched on periodically based on a digital signal coming from the connection matrix. when acmp i s powered down, output is low. each of the acmp cells has a positive input signal that can be provided by a variety of exter nal sources, and can also have a selectable gain stage before connection to the analog comparato r. each of the acmp cells has a negative input signal that is either created from an internal v ref or provided by way of the external sources. each of the acmp cells has a selection for the bandwidth of the input signal, which can be used to save power when low bandwid th signals are input into the analog comparator. and if input freq uency > 200 khz, the output will retain its previous value. eac h cell also has a hysteresis selection , to offer hysteresis of 0 mv, 2 5 mv, 50 mv or 200 mv. during powerup, the acmp output will remain low, and then becom e valid 110 s (max) after por signal goes high, see figure 19 . note: regulator and charge pump set to automatic on/off. each of the acmp cells has a positive input signal that can be provided by a variety of exter nal sources, and can also have a selectable gain stage (1x, 0.5x, 0.33x, 0.25x) before connectio n to the analog comparator. the gain divider is unbuffered and consists of 250 k? (typ.) resistors, see table 36 . for gain divider accuracy refer to table 37 . in- voltage range: 0 - 1.2 v. can use vref selection v dd/4 and vdd/3 to maint ain this input range . figure 19. maximum power on delay vs. vdd. table 36. gain di vider input resistance (typ). gain 1x 0.5x 0.33x 0.25x input resistance 100m 1m 0.75m 1m table 37. gain di vider accuracy. gain 0.5x 0.33x 0.25x accuracy 0.6% 0.9% 2.8% 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 power on delay (s) 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 1 0 2 0 1.71 1.80 1.89 2.50 2.70 3.00 330 vdd (v) 3 . 30 3.60 4.20 4.50 -4 0 ro o +8 5 5.00 5.50 0 ? c o m 5 ? c
000-0046110-106 page 45 of 81 slg46110 each of the acmp cells has a negative input signal that is eith er created from an internal vref or provided by the external reference/source. in ternal vref accuracy is optimized near 1000 mv selection. note: power supply control options ha ve influence on the acmp operation. note: any acmp powered on enables the bandgap internal circui t as well. an analog voltage will appear on vref (even when the force bandgap option is set as disabled). analog comparators have the f ollowing configurable options: ? hysteresis: input signal hyster esis options are disable, 25 mv , 50 mv, 200 mv. ? low bandwidth: enable, disable; ? in+ gain: 1x, 0.5x, 0.33x, 0.25x; ? in+ source: ? acmp0 in+ options are pin 3, vdd; ? acmp1 in+ options are pin 6, acmp0 in+; ?in- source: ? acmp0 in- options are 24 internal reference sourc es (50 mv C 1 200 mv) and vdd/3, vdd/4, pin 4; ? pwr up=0 C acmp is powered down; pwr up=1 C acmp is powered up . all acmps can have a common negat ive input. this can be achieve d by configuring acmp0 pi n 4 analog i/o connection. 11.1 acmp0 block diagram figure 20. acmp0 block diagram 11010 11001- 00000 internal vref pin4: acmp0(-) 10 01 pin3: acmp0(+) external vdd 1.71 v ~ 5.5 v selectable gain reg <364:363> to acmp1 mux input vref + - from connection matrix output <12> pdb lbw selection ibias reg <365> hysteresis selection reg <362:361> l/s on after 100 ? s delay to connection matrix input<19> reg <360:356> *pin3_aio_en; reg <366> off after 1 ? s delay *pin3_aio_en: if reg <385:383> = 011 then 1, otherwise: 0
000-0046110-106 page 46 of 81 slg46110 11.2 a cmp0 register settings table 38. acmp0 register settings signal function register bit address register definition acmp0 in voltage select reg <360:356> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 0 1101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref (pin4) acmp0 hysteresis enable reg <362:361> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) acmp0 positive input divider reg <364:363> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp0 low bandwidth (max: 1 mhz) enable reg <365> 0: off 1: on acmp0 positive input source select pin3 and vdd reg <366> 0: pin3 1: vdd
000-0046110-106 page 47 of 81 slg46110 11.3 acmp1 block diagram figure 21. acmp1 block diagram 11010 11001- 00000 internal vref pin4: acmp0(-) 10 01 pin6: acmp1(+) from acmp0s mux selectable gain reg <375:374> vref + - from connection matrix output <36> pdb lbw selection ibias reg <377> hysteresis selection reg <373:372> l/s on after 100 ? s delay to connection matrix input<20> reg <371:367> *pin6_aio_en; reg <378> off after 1 ? s delay *pin6_aio_en: if reg <19:15> = 00000 and reg <398:397> = 11 then 1, other wise: 0
000-0046110-106 page 48 of 81 slg46110 11.4 acmp1 register settings table 39. acmp1 register settings signal function register bit address register definition acmp1 in voltage select reg <371:367> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 0 1101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref (pin4) acmp1 hysteresis enable reg <373:372> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) acmp1 positive input divider reg <375:374> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp1 low bandwidth (max: 1 mhz) enable reg <377> 1: on 0: off acmp1 positive input source select pin3 and pin6 reg <378> 0: pin6 1: pin3
000-0046110-106 page 49 of 81 slg46110 11.5 typical performance characteristics note: when vdd < 1.8v voltage reference should not exceed 1100 mv. figure 22. typical input voltage offset vs. voltage reference a t room temperature, lbw mode C disable, vhys=0 mv, vdd=(1.7 C 5.5) v. figure 23. typical input threshold variation (including vref var iation, acmp offset) vs. voltage reference at room temper ature, lbw mode C disable, vhys =0 mv. -5 -4 -3 -2 -1 0 1 2 3 4 5 50 150 250 350 450 550 650 750 850 950 1050 1150 voffset (mv) voltage reference (mv) upper limit lower limit -6% -4% -2% 0% 2% 4% 6% 8% 50 150 250 350 450 550 650 750 850 950 1050 1150 input threshold variation (%) voltage reference (mv) upper limit @ vdd=(1.8-5.5)v lower limit @ vdd=(1.8-5.5)v upper limit @ vdd=1.7v lower limit @ vdd=1.7v
000-0046110-106 page 50 of 81 slg46110 figure 24. input threshold ratio vs . voltage reference at vdd = (1.71 - 5.5) v, vh ys = 0, gain = 1 figure 25. input threshold voltage vih, vil vs. vdd at vref = 10 00 mv, gain = 1 -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 50 100 200 300 400 500 600 700 800 900 1000 1100 1200 input threshold (%) voltage reference (mv) low-to-high @ +85c high-to-low @ +85c low-to-high @ -20c high-to-low @ -20c -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 1.71 2.5 3 5.5 input threshold voltage vih, vil (mv) vdd (v) vih @ +85oc vih @ -35oc vil @ +85oc vil @ -35oc
000-0046110-106 page 51 of 81 slg46110 figure 26. input threshold voltage vih, vil vs. hysteresis at vd d = 5.5 v, vref = 1000 mv. gain = 1 figure 27. input threshold voltage vih, vil vs. gai n at hysteres is = 0, vdd = 5.5 v, vref = 1000 mv table 40. built-in hy steresis tolerance. vhys (mv) vdd=(1.7-1.8) v vdd=(1.89-5.5) v vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv min max min max min max min max min max min max 25 18.9 26.4 17.3 26.1 13.0 24.6 18.8 26.5 17.8 26.1 15.6 25.5 50 40.3 50.4 37.9 50.1 28.9 47.7 40.3 50.5 39.5 50.1 34.5 49.5 200 180.5 208.4 172.9 210.7 153.5 217.2 180.6 207.7 180.2 210.8 166.5 211.9 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 0 25 50 200 input threshold voltage vih, vil (mv) hysteresis (mv) vih @ +85oc vih @ -35oc vil @ +85oc vil @ -35oc -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 1 0.5 0.33 0.25 input threshold voltage vih, vil (mv) gain vih @ +85oc vih @ -35oc vil @ +85oc vil @ -35oc
000-0046110-106 page 52 of 81 slg46110 11.6 timing characteristics figure 28. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vod = 2 mv. figure 29. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vdd=(1.71 C 1.89) v. 0 5 10 15 20 25 30 35 40 45 50 55 60 50 propagation delay low-to-hogh (s) 150 250 350 450 vol t vdd= vdd= 3 vdd= 5 450 550 650 750 t age referenc e 1.7 v 3 .3 v 5 .5 v 850 950 1050 1150 e (mv) 1150 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 figure 30. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vod = 2 mv. figure 31. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vdd=(1.71 C 1.89) v. 0 5 10 15 20 25 30 35 40 45 50 55 60 50 propagation delay high-to-low (s) 150 250 350 450 volt a vdd= 3 vdd= 5 vdd= 1 550 650 750 ge reference ( 3 .3 v 5 .5 v 1 .7 v 850 950 1050 1150 ( mv) 1150 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200
000-0046110-106 page 53 of 81 slg46110 figure 32. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vdd = (1.89 C 3.6) v. figure 33. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vdd = (3.6 C 5.5) v. 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 figure 34. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vdd = (1.89 C 3.6) v. figure 35. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vdd = (3.6 C 5.5) v. 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200
000-0046110-106 page 54 of 81 slg46110 12.0 counters/delay generators (cnt/dly) there are three configurable c ounters/delay generators in the s lg46110. the three counters/delay generators (cnt/dly 0, 1, 3) are 8-bit. for flexibility, each of these macrocells has a l arge selection of internal and ex ternal clock sources, as well as the option to chain from t he output of th e previous (n-1) cnt/dly m acrocell, to implement lo nger count / delay circuits. two of the counter/delay generat or macrocells (cnt/dly0 and cnt /dly1) have two inputs from t he connection matrix, one for delay input/reset input (delay_in/reset_in), and one for an ext ernal counter/clock source. one of the counter/delay generator macrocells (cnt/dly3) has one input from the connection matrix, which has a shared function of either a delay input or an external clock input. note that there is also one combination function macrocells tha t can implement either 4-bit lut s or 8-bit counter / delays, fo r more information please see section 10.4 4-bit lut or 8- bit co unter / delay macrocells. figure 36. cnt/dly0 cnt/dly0 counter_end clk to connection matrix input <16> from connection matrix output <31> count_end_out_x-1 reg <314> 0 1 2 3 4 5 6 7 ext. clock from cm out<33> rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <325:318> reg <317:315> 0 1 0 1 delay_out delay_in cnt clock
000-0046110-106 page 55 of 81 slg46110 figure 37. cnt/dly1 figure 38. cnt/dly3 cnt/dly1 counter_end clk to connection matrix input <17> from connection matrix output <32> count_end_out_x-1 reg <328> 0 1 2 3 4 5 6 7 ext. clock from cm out<33> rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <339:332> reg <331:329> 0 1 0 1 delay_out delay_in reset_in edge detector cnt/dly3 counter_end clk to connection matrix input <18> from connection matrix output <34> count_end_out_x-1 reg <342> 0 1 2 3 4 5 6 7 ext. clock rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <353:346> reg <345:343> 0 1 0 1 delay_out delay_in/cnt_ext_clk delay_in cnt clock edge detector
000-0046110-106 page 56 of 81 slg46110 12.1 cnt/dly0 register settings 12.2 cnt/dly1 register settings table 41. cnt/dly0 register settings signal function register bit address register definition counter/delay0 mode select reg <314> 0: delay mode 1: counter mode counter/delay0 clock source select (external clock is only for counter mode) reg <317:315> 000: i nternal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter3 overflow counter0 control data/delay0 time control reg <325:318> 1-256: (delay time = (counter control data +2) /fr eq) delay0 mode select or asynchronous counter reset reg <327:326> 00: delay on both f alling and risi ng edges(for del ay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode table 42. cnt/dly1 register settings signal function register bit address register definition counter/delay1 mode select reg <328> 0: delay mode 1: counter mode counter/delay1 clock source select (external clock is only for counter mode) reg <331:329> 000: i nternal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter0 overflow counter1 control data/delay1 time control reg <339:332> 1-256: (delay time = (counter control data +2) /fr eq) delay1 mode select or asynchronous counter reset reg <341:340> 00: delay on both f alling and risi ng edges(for del ay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode
000-0046110-106 page 57 of 81 slg46110 12.3 cnt/dly3 register settings table 43. cnt/dly3 register settings signal function register bit address register definition counter/delay3 mode select reg <342> 0: delay mode 1: counter mode counter/delay3 clock source select (external clock is only for counter mode) reg <345:343> 000: i nternal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: reserved counter3 control data/delay3 time control reg <353:346 1-256: (delay time = (counter control data +2) /fre q) delay3 mode select reg <355:354> 00: delay on both falling and r ising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges
000-0046110-106 page 58 of 81 slg46110 13.0 voltage reference (vref) 13.1 voltage reference overview the slg46110 has a voltage reference macrocell to provide refer ences to the two analog compar ators. this macrocell can supply a user selectio n of fixed voltage references, /3 and /4 reference off of the v dd power supply to the dev ice, and externally supplied voltage references from pin 4. the macrocell also has the option to output reference voltages on pin 10. see table be low for the available selections for each analog comparator. also s ee figure 39 below, which shows the re ference output structure. 13.2 vref selection table table 44. vref selection table. sel<4:0> cmp0_vref cmp1_vref 11010 ext. vref (pin4) ext. vref (pin4) 11001 vdd / 4 vdd / 4 11000 vdd / 3 vdd / 3 10111 1.20 v 1.20 v 10110 1.15 v 1.15 v 10101 1.10 v 1.10 v 10100 1.05 v 1.05 v 10011 1.00 v 1.00 v 10010 0.95 v 0.95 v 10001 0.90 v 0.90 v 10000 0.85 v 0.85 v 01111 0.80 v 0.80 v 01110 0.75 v 0.75 v 01101 0.70 v 0.70 v 01100 0.65 v 0.65 v 01011 0.60 v 0.60 v 01010 0.55 v 0.55 v 01001 0.50 v 0.50 v 01000 0.45 v 0.45 v 00111 0.40 v 0.40 v 00110 0.35 v 0.35 v 00101 0.30 v 0.30 v 00100 0.25 v 0.25 v 00011 0.20 v 0.20 v 00010 0.15 v 0.15 v 00001 0.10 v 0.10 v 00000 0.05 v 0.05 v vdd practial vref range note 2.0 v - 5.5 v 50 mv ~1.2 v 1.7 v - 2.0v 50 mv ~1.1 v higher t han 1.1 v negativ e input, the c omparator may show wrong result
000-0046110-106 page 59 of 81 slg46110 13.3 vref block diagram figure 39. voltage refe rence block diagram cmp0_vref cmp1_vref reg <360:356> reg <371:367> vdd / 3 vdd / 4 ext_vref_acmp0 (pin4) reg <445> forced bg on 000 001 100 101 110 reg <452> vdd / 2 vdd / 3 vdd / 4 reg <449:447> 1 0 op reg <446> vref out_1 (pin10) pin10_aio_en external vdd 2.7 v - 5.5 v
000-0046110-106 page 60 of 81 slg46110 14.0 rc oscillator (rc osc) 14.1 rc oscillator overview the slg46110 has two internal rc oscillators, one that runs at 25 khz and one that runs at 2 mhz . when using the chip internal rc osc, a choice is available to force power on, meaning that the rc osc will always run, or auto power on, meaning that the rc osc will have an associat ed startup and settling time as sociated with it (offset). figure 40 and figure 41 show maximum power on delay vs. vdd. note: rc osc power setting: "auto power on?. figure 40. maximum power on del ay vs. vdd, rc osc = 2 mhz. figure 41. maximum power on del ay vs. vdd, rc osc = 25 khz.
000-0046110-106 page 61 of 81 slg46110 the user can select one of these fundamental frequencies for th e rc osc macrocell, or the f undamental frequency can also come from an external clock input (pin 12). there are two divid er stages that allow the user flexibility for introducing clock signals on various connection matrix input lines. the first stage divid er (also known as the clock pre-divider) allows the selection o f /1, /2, /4 or /8 divide down frequency from the fundamental. there are two second stage divider controls (out0 and out1). each has its own input of one frequency from the first stage divider , and outputs two different frequencies on connection matrix in put lines <23>, and <24>. see figure 42 below for details of the frequencies for e ach of these two con nection matrix inputs. if pwr down input of oscillator is low, the oscillator will be turned on. if pwr down input of oscillator is high the oscillat or will be turned off. the pwr down signal has the highest priorit y. 14.2 rc osc bl ock diagram figure 42. rc osc block diagram internal rco reg <303> 0: 25 khz 1: 2 mhz / 2 / 3 / 4 / 8 / 12 / 24 / 64 to connection matrix input <23> reg <308:306> div /1/2/4/8 reg <305:304> clock pre- divider control second stage divider pin 12 ext. clock ext. clk sel reg <312> 0 1 reg <311:309> to connection matrix input <24> from connection matrix output <38> pwr down out0 out1
000-0046110-106 page 62 of 81 slg46110 15.0 power on rest (por) the slg46110 has a power-on reset (por) macrocell to ensure cor rect device initialization and operation of all macrocells in t he device. the purpose of the por circuit is to have consistent be havior and predictable results when the vdd power is first ramp ing to the device, and also while the vdd is falling during power-d own. to accomplish this goal, the por drives a defined sequence of internal events that trigger changes to the states of differ ent macrocells inside the device, and finally to the state of t he i/o pins. this application note is created to explain the whole process o f por operation and greenpak chip behavior during the time whil e it is powering up and powering down. 15.1 general operation the slg46110 is guaranteed to be powered down and nonoperationa l when the vdd voltage (voltage on pin1) is less than 0.6v, but not less than -0.6v. another essential condition for the ch ip to be powered down is that no voltage higher (see note 1) th an the vdd voltage is applied to any other pin. for example, if vd d voltage is 0.3v, applying a voltage higher than 0.3v to any o ther pin is incorrect, and can lead t o incorrect or unexpected devic e behavior. note 1. there is a 0.6v margin due to forw ard drop voltage of t he esd protection diodes. to start the por sequence in the slg46110, the voltage applied on the vdd should be higher than the power_on threshold (see note 2). the full operational vdd range for the slg46110 i s 1.71v C 5.5v (1.8v 5% - 5v 10%). this means that the vdd voltage must ramp up to the operational voltage value, but the por sequence will start earlier, as soon as the vdd voltage ris es to the power_on threshold. after the por sequence has started, the slg46110 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the por sequence is complete. note 2. the power_on threshold can vary by pvt, but typically it is 1.6v. to power down the chip the vdd voltage should be lower than the operational and to guarantee that chip is powered down it should be less than 0.6v. all pins are in high impedance st ate when the chip is powered d own and while the por sequence is taking place. the last step in the por sequence releases the i/o structures from the high i mpedance state, at which time the device is operational. the pi n configuration at this point in time is defined by the design pr ogrammed into the chip. also as it was mentioned before the vol tage on pins cant be bigger than t he vdd, this rule also applies to the case when the chip is powered on.
000-0046110-106 page 63 of 81 slg46110 15.2 por sequence the por system generat es a sequence of signa ls that enable cert ain macrocells. the sequence is shown in figure 43 . as can be seen from figure 43 after the vdd has start ramping up and crosses the power_on th reshold, first, the on-chip nvm memory is reset. next the chip reads the data from nvm, and tra nsfers this information to sram registers that serve to configu re each macrocell, and the connection matrix which routes signals between macrocells. the third stage causes the reset of the inp ut pins, and then to enable them. after that, the luts are reset a nd become active. after luts the delay cells, rc osc, dffs, latches and pipe delay are initialized. only after all macrocel ls are initialized internal por s ignal (por macrocell output) g oes from low to high. the last portion of the device to be initiali zed are the output pins, which transition from high impedience to active at this point. the typical time that takes to complete the por sequence varies by device type in the greenpak family. it also depends on many environmental factors, such as: slew rate, vdd value, temperatu re and even will vary from chip to chip (process influence). figure 43. por sequence vdd por_nvm (reset for nvm) nvm_ready_out por_gpi (reset for input enable) por_lut (reset for lut output) por_core (reset for dly/rc osc/dff /latch/pipe dly/other macrocells por_out (generate low to high to matrix) por_gpo (reset for output enable) t t t t t t t t tsu
000-0046110-106 page 64 of 81 slg46110 15.3 macrocells output states during por sequence to have a full picture of slg46110 operation during powering an d por sequence, review the overview the macrocell output states during the por sequence ( figure 44 describes the output signals states). first, before the nvm has been res et, all macrocells have their output set to logic low (exc ept the output pins which are in h igh impedance state). before the nv m is ready, all macrocell output s are unpredictable (except the output pins). on the next step, some of the macrocells start ini tialization: input pins output state becomes low; luts also output low. only p dly macrocell configured as edge detector becomes active at this time. after that input pins are enabled. next, only luts are configured. ne xt, all other macrocells are initialized. after macrocells are init ialized, internal por matrix signa l switches from low to high. the last are output pins that become active and determined by the i nput signals. figure 44. internal macrocell states during por sequence unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable vdd input pin_out to matrix lut_out to matrix programmable delay_out to matrix prog. edge_detector_out to matrix dff/latch_out to matrix delay_out to matrix por_out to matrix ext. gpo vdd_out to matrix determined by input signals determined by input signals starts to detect input edges determined by input signals determined by input signals determined by input signals starts to detect input edges determined by input signals determined by external signal guaranteed high before por_gpi determined by input signals out = in without delay determined by initial state determined by input signals out = in without delay tri-state t t t t t t t t t t
000-0046110-106 page 65 of 81 slg46110 16.0 appendix a - slg46110 register definition register bit address signal function register bit definition reg <4:0> matrix out: pin3 digital output source reg <9:5> matrix out: pin4 digital output source reg <14:10> matrix out: pin6 digital output source reg <19:15> matrix out : output enable of pin6 reg <24:20> matrix out: in0 of lut2_0 or clock input of dff0 reg <29:25> matrix out: in1 of lut2_0 or data input of dff0 reg <34:30> matrix out: in0 of lut2_1 or clock input of dff1 reg <39:35> matrix out: in1 of lut2_1 or data input of dff1 reg <44:40> matrix out: in0 of lut2_2 reg <49:45> matrix out: in1 of lut2_2 reg <54:50> matrix out: in0 of lut2_3 reg <59:55> matrix out: in1 of lut2_3 reg <64:60> matrix out: in0 of lut3_0 or clock input of dff2 reg <69:65> matrix out: in1 of lut3_0 or data input of dff2 reg <74:70> matrix out: in2 of lut3_0 or resetb input of dff2 reg <79:75> matrix out: in0 of lut3_1 or clock input of dff3 reg <84:80> matrix out: in1 of lut3_1 or data input of dff3 reg <89:85> matrix out: in2 of lut3_1 or resetb(setb) of dff3 reg <94:90> matrix out: in0 of lut3_2 reg <99:95> matrix out: in1 of lut3_2 reg <104:100> matrix out: in2 of lut3_2 reg <109:105> matrix out: in0 of lut3_3 reg <114:110> matrix out: in1 of lut3_3 reg <119:115> matrix out: in2 of lut3_3 reg <124:120> matrix out: in0 of lut3_4 or input of pipe delay reg <129:125> matrix out: in1 of lut3_4 or resetb of pipe delay reg <134:130> matrix out: in2 of lut3_4 or clock of pipe delay reg <139:135> matrix out: in0 of lut4_0 or input for delay2 (counter2) external clock reg <144:140> matrix out: in1 of lut4_0 o r input for delay2 data (counter2 reset) reg <149:145> matrix out: in2 of lut4_0 reg <154:150> matrix out: in3 of lut4_0 reg <159:155> matrix out: input f or delay0 data (c ounter0 reset) reg <164:160> matrix out: input f or delay1 data (c ounter1 reset) reg <169:165> matrix out: input for delay 0/1 (counter0/1) external clock reg <174:170> matrix out: input f or delay3 (counter3) external c lock reg <179:175> matrix out: pdb(power down) for acmp0 reg <184:180> matrix out: pdb(power down) for acmp1 reg <189:185> matrix out: input for programmable delay (deglitch filter input)
000-0046110-106 page 66 of 81 slg46110 reg <194:190> matrix out: power down for osc reg <199:195> matrix out: pin 8 digital output source reg <204:200> matrix out: pin 9 digital output source reg <209:205> matrix out: pin 10 digital output source reg <214:210> matrix out: output enable of pin10 reg <219:215> matrix out: pin 12 digital output source reg <223:220> reserved reserved dff0/latch reg <227:224> reg <224> dff0 or latch select 0: dff function 1: latch function reg <225> dff0 output select 0: q output 1: nq output reg <226> dff0 initi al polarity select 0: low 1: high reg <227> unused if dff/latch selected unused dff1/latch reg <231:228> reg <228> dff1 or latch select 0: dff function 1:latch function reg <229> dff1 output select 0: q output 1: nq output reg <230> dff1 initi al polarity select 0: low 1:high reg <231> unused if dff/latch selected unused lut2_2 data reg <235:232> lut2_2 data lut2_2 data lut2_1 data reg <239:236> lut2_1 data lut2_1 data lut2_0/dff0 reg <240> lut2_0 or dff0 select 0: lut2_0 1: dff0 lut2_1/dff1 reg <241> lut2_1 or dff1 select 0: lut2_1 1: dff1 lut3_0 or dff2/latch reg <249:242> reg <242> dff2 or latch select 0: dff function 1: latch function reg <243> dff2 output select 0: q output 1: nq output reg <244> dff2 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg <245> dff2 initial polarity select 0: low 1: high reg <249:246> unused if df f/latch selected unused register bit address signal function register bit definition
000-0046110-106 page 67 of 81 slg46110 lut3_1 or dff3/latch reg <257:250> reg <250> dff3 or latch select 0: dff function 1: latch function reg <251> dff3 output sel ect 0: q output 1: nq output 0: q output 1: nq output reg <252> dff3 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg <253> dff3 initial polarity select 0: low 1: high reg <257:254> unused if df f/latch selected unused lut3_2 data reg <265:258> lut3_2 data lut3_2 data lut3_3 data reg <273:266> lut3_3 data lut3_3 data lut3_4 or pipe number select reg <281:274> reg <276:274>: out0 select data (pipe number) reg <279:277>: out1 select data (pipe number) reg <281:280>: unused if p ipe delay selected unused lut3/dff select reg <282> lut3_0 or dff2 select 0: lut3_0 1: dff2 reg <283> lut3_1 or dff3 select 0: lut3_1 1: dff3 reg <284> lut3_4 or pipe delay output select 0: lut3_4 1: pipe delay lut4_0 or counter/delay2 mode selection reg <300:285> reg <285> counter/delay2 mode selection 0: delay mode 1: counter mode reg <288:286> counter/del ay2 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter1 overflow reg <296:289> counter/delay2 cont rol data 1 C 256 (delay time = (counter control data +2) /freq) reg <298:297> delay2 mode select or asynchronous counter reset 00: delayon both falling and rising edges(for delay & counter reset) 01: delayon falling edge only (for delay & counter resedelayt) 10: on rising edge only (for delay & counter reset) 11: no delay on either falli ng or rising edges / high level reset for counter mode reg <300:299> unused is counter/delay2 selected unused reg <301> lut4_0 or counter2 select 0: lut4_0, 1: counter2 0: lut4_0 1: counter2 reg <302> force rc oscillator on 0: auto power on 1: force power on register bit address signal function register bit definition
000-0046110-106 page 68 of 81 slg46110 reg <303> rc oscillator frequency control 0: 25k 1: 2m reg <305:304> osc cl ock pre-divider 00: div1 01: div2 10: div4 11: div8 reg <308:306> internal oscillator frequency divider control 0 for matrix input 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 reg <311:309> internal oscillator frequency divider control 1 for matrix input 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 reg <312> external clock source select 0: internal oscillator 1: external clock from pin12 reg <313> reserved reserved counter/delay 0 reg <327:314> reg <314>counter/delay0 mode selection 0: delay mode 1: counter mode reg <317:315> counter/del ay0 clock source select (external clock is o nly for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter3 overflow reg <325:318> counter0 control data/delay0 time control 1-256: (delay time = (coun ter control data +2) /freq) reg <327:326> delay0 mode select or asynchronous counter reset 00: delayon both falling and rising edges(for delay & counter reset) 01: delayon falling edge only (for delay & counter reset) 10: delayon rising edge only (for delay & counter reset) 11: no delay on either falli ng or rising edges / high level reset for counter mode register bit address signal function register bit definition
000-0046110-106 page 69 of 81 slg46110 counter/delay 1 reg <341:328> reg <328> counter/delay1 mode selection 0: delay mode 1: counter mode reg <331:329> counter/del ay1 clock source select (external clock is o nly for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter0 overflow reg <339:332> counter1 control data/delay1 time control 1-256: (delay time = (coun ter control data +2) /freq) reg <341:340> delay1 mode select or asynchronous counter reset 00: delay on both falling and rising edges(for delay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge onl y (for delay & counter reset) 11: no delay on either falli ng or rising edges / high level reset for counter mode counter/delay 3 reg <355:342> reg <342> counter/delay3 mode selection 0: delay mode 1: counter mode reg <345:343> counter/del ay3 clock source select (external clock is o nly for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter2 overflow reg <353:346> counter3 control data/delay4 time control 1-256: (delay time = (coun ter control data +2) /freq) reg <355:354> delay3 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either f alling or rising edges register bit address signal function register bit definition
000-0046110-106 page 70 of 81 slg46110 acmp0 reg <366:356> reg <360:356> acmp0 in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin4) reg <362:361> acmp0 hysteresis enable 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) reg <364:363> acmp0 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <365> acmp0 low band width (typ: max.1mhz) en- able. 0: off 1: on reg <366> acmp0 positive input source select pin3 and vdd 0: pin3 1: vdd register bit address signal function register bit definition
000-0046110-106 page 71 of 81 slg46110 acmp1 reg <378:367> reg <371:367> acmp1 in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin4) reg <373:372> acmp1 hysteresis enable 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) reg <375:374> acmp1 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <376> acmp1 100ua current source option 0: disable 1: enable reg <377> acmp1 low bandwidth (typ: max.1 mhz) en- able. 0: off 1: on reg <378> acmp1 positive input source select pin6 and pin3 0: pin6 1: pin3 pin 2 reg <382:379> reg <380:379> pin2 mode control 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved reg <382:381> pin2 pull down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m register bit address signal function register bit definition
000-0046110-106 page 72 of 81 slg46110 pin 3 reg <389:383> reg <385:383> pin3 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input / output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input / output & open drain reg <387:386> pin3 pull up/do wn resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m reg <388> pin3 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <389> pin3 driver strength selection 0: 1x 1: 2x pin 4 reg <396:390> reg <392:390> pin4 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input / output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input / output & open drain reg <394:393> pin4 pull up/do wn resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m reg <395> pin4 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <396> pin4 driver strength selection 0: 1x 1: 2x pin6 reg <403:397> reg <398:397> pin6 mode control (sig_pin6_oe =0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 11: low voltage digital input 10: analog in put / output reg <400:399> pin6 mode control (sig_pin6_oe =1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x reg <402:401> pin6 pull up/do wn resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m reg <403> pin6 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable register bit address signal function register bit definition
000-0046110-106 page 73 of 81 slg46110 pin8 reg <410:404> reg <406:404> pin8 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input / output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input / output & open drain reg <408:407> pin8 pull up/do wn resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m reg <409> pin8 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <410> pin8 driver strength selection 0: 1x 1: 2x pin9 reg <417:411> reg <413:411> pin9 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input / output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input / output & open drain reg <415:414> pin9 pull down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg <416> pin9 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <417> pin9 driver strength selection 0: 1x 1: 2x pin10 reg <424:418> reg <419:418> pin10 mode control (sig_pin10_oe =0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 11: low voltage digital input 10: analog in put / output reg <421:420> pin10 mode control (sig_pin10_oe =1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x reg <423:422> pin10 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m reg <424> pin10 pull up/ down resistor select 0: pull down resistor enable 1: pull up resistor enable register bit address signal function register bit definition
000-0046110-106 page 74 of 81 slg46110 pin12 reg <431:425> reg <427:425> pin12 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input / output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input / output & open drain reg <429:428> pin12 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m reg <430> pin12 pull up/ down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <431> pin12 driver strength selection 0: 1x 1: 2x reg <432> pipe delay out 1 polarity select bit 0: non-inverting 1: inverting reg <440:433> 8-bit pattern id 8-bit pattern id reg <441> filter0 output polarity select 0: non-inverting 1: inverting reg <443:442> reserved reserved reg <444> gpio quick charge enable 0: disable 1: enable reg <445> force bandgap on 0: auto-mode 1: enable reg <446> vref1 output active buffer control 0: disabled 1: enabled reg <449:447> vref1 output source select 000: acmp0 reference voltage 001: acmp1 reference voltage 100: vdd/2 101: vdd/3 110: vdd/4 101: reserved 110: reserved 111: reserved reg <450> nvm data read disable 0: disable (read enable) 1: enable (read disable) reg <451> nvm power down (or nvm data programming disable) 0: none (or programming enable) 1: power down (or pr ogramming disable) reg <452> power divider power 0: power down 1: power on reg <453> por auto power detect 0: enable 1: disable reg <454> charge pump for analog macrocell enable (when vdd <= 2.7 v turn on) 0: disable (automat ic on/off control) 1: enable (always on) reg <455> vdd bypass enable 0: regulator auto on 1: regulator off (vdd bypass)" reg <471:456> reserved reserved reg <479:472> reserved reserved register bit address signal function register bit definition
000-0046110-106 page 75 of 81 slg46110 reg <481:480> reserved reserved reg <482> pin2 edge detect mode 0: rising edge 1: falling edge reg <483> bypass the pin2 0: pin2 edge active 1: pin2 high active reg <484> pin2 reset enable 0: disable 1: enable reg <485> programmable delay or filter output select 0: programmable delay output 1: filter output reg <487:486> select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay reg <489:488> delay value select for pro grammable delay & edge de- tector (vdd = 3.3 v, typical condition) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns reg <490> reserved reserved reg <495:491> reserved reserved reg <501:496> reserved reserved reg <502> reserved reserved reg <503> reserved reserved reg <511:504> reserved reserved register bit address signal function register bit definition
000-0046110-106 page 76 of 81 slg46110 17.0 package top marking system definition p p a part code + assembly code pin 1 identifier wwr date code + revision code nn serial number code
000-0046110-106 page 77 of 81 slg46110 18.0 package drawing and dimensions 12 lead stqfn fc p ackage 1.6 x 1.6 mm ic net weight: 0.0028 g
000-0046110-106 page 78 of 81 slg46110 19.0 tape and reel specifications 19.1 carrier tape drawing and dimensions package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 12l fc 0.4p green 12 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4 package type pocket btm length [mm] pocket btm width [mm] pocket depth [mm] index hole pitch [mm] pocket pitch [mm] index hole diameter [mm] index hole to tape edge [mm] index hole to pocket center [mm] tape width [mm] a0 b0 k0 p0 p1 d0 e f w stqfn 12l fc 0.4p green 1.9 1.9 0.8 4 4 1.5 1.75 3.5 8
000-0046110-106 page 79 of 81 slg46110 20.0 recommended land pattern 21.0 recommended reflow soldering profile please see ipc/jedec j-std-020: l atest revision for reflow prof ile based on package volume of 1.408 mm 3 (nominal). more information can be f ound at www.jedec.org. units: ? m
000-0046110-106 page 80 of 81 slg46110 22.0 revision history date version change 10/10/2017 1.06 updated electrical spec fixed typos updated por sequence 7/7/2017 1.05 fixed typos removed references to gpak families updated silego w ebsite & support updated section programmable delay / edge detector updated electrical spec 5/27/2016 1.04 updated programmable delay information added pon thr and poff thr in electrical spec 4/4/2016 1.03 correc ted section 6.0 10/28/2015 1.02 updated abso lute maximum conditions 9/29/2015 1.01 fixed typos 5/26/2016 1.0 production release 5/21/2015 0.66 updated acmp diagram s and added timing characteris tics diagrams 4/23/2015 0.65 updated acmp section 4/9/2015 0.64 updated tsu condition and value 3/27/2015 0.63 updated acmp section updated rc oscillator section 3/16/2015 0.62 updated re gister table (typos) 3/10/2015 0.61 added con nection matrix example 3/9/2015 0.60 added por section 1/14/2015 0.59 added idd estimator, timing estimator, expected de lays sections 12/3/2014 0.58 updated electrical c haracteristics vi h/vil/voh/vol values (formatting/rounding) 9/3/2014 0.57 updated el ectrical characteris tics vih/vil/voh/vol values 8/25/2014 0.56 added re commended land pattern 7/23/2014 0.55 fixed esd information 6/20/2014 0.54 fixed ty po on electrical spec 5/21/2014 0.53 updated block diagram fixed typos moved programmable delay and deg litch filter to combination mac rocells section 4/29/2014 0.52 added esd r atings and msl to absolute maximum cond itions 3/28/2014 0.5 fixed typos preliminary release 3/18/2014 0.42 updated bl ock diagrams and timin g diagrams for cla rity 2/12/2014 0.41 fixed typos 12/2/2013 0.40 updated vih/vil in elect rical characteristics fixed typos added ic net weight to package specification 11/25/2013 0.31 added block diagram 11/11/2013 0.30 added diagrams 9/30/2013 0.20 updated electrical characteristics added register table and descriptions 9/16/2013 0.10 initial release
000-0046110-106 page 81 of 81 slg46110 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding si lego green products, please vi sit our website. our green product lines feature: greenpak: programmable mixed signal matrix products greenfet1 / greenfet3 / hfet1: mos fet drivers and ultra-small, low rdson load switches greenclk1 / greenclk2 / greenclk 3: crystal replacement technolo gy products are also available for purchase directly from silego a t the silego on line store at http://store.silego.com/ . silego technical support datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions and supp ort please send e-mail requests to greenpak@silego.com users of silego products can rec eive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for support. local sales offices ar e also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted d irectly via e-mail at info@silego.com or user submission form, l ocated at the f ollowing url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminar s and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer m arket. applications or uses as critical components in life support devices or systems are n ot authorized. silego technolog y does not assume any liability arising out of such applica- tions or uses of its products. silego technology reserves the r ight to improve product design , functions and reliability without notice .

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